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Anglický jazyk
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Autor: Krishnendu Chakrabarty
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results... Viac o knihe
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O knihe
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
- Vydavateľstvo: Springer International Publishing
- Rok vydania: 2016
- Formát: Paperback
- Rozmer: 235 x 155 mm
- Jazyk: Anglický jazyk
- ISBN: 9783319345345
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