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Anglický jazyk
Design of High Speed and Low Power Configurable Booth Multiplier
Autor: K. Shashidhar
A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can... Viac o knihe
Na objednávku
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O knihe
A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation.
- Vydavateľstvo: LAP LAMBERT Academic Publishing
- Rok vydania: 2021
- Formát: Paperback
- Rozmer: 220 x 150 mm
- Jazyk: Anglický jazyk
- ISBN: 9786204197654
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