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Anglický jazyk
Verilog and SystemVerilog Gotchas
Autor: Don Mills
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.... Viac o knihe
Na objednávku
158.39 €
bežná cena: 175.99 €
O knihe
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
- Vydavateľstvo: Springer US
- Rok vydania: 2007
- Formát: Hardback
- Rozmer: 241 x 160 mm
- Jazyk: Anglický jazyk
- ISBN: 9780387717142
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