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Anglický jazyk
Constraining Designs for Synthesis and Timing Analysis
Autor: Sanjay Churiwala
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted... Viac o knihe
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O knihe
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
- Vydavateľstvo: Springer New York
- Rok vydania: 2015
- Formát: Paperback
- Rozmer: 235 x 155 mm
- Jazyk: Anglický jazyk
- ISBN: 9781489989161
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