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Anglický jazyk
Design and Implementation of a Multicore Processor Using FPGA
Autor: Ali J. Ibada
This book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS processor is designed using VHDL, which can execute 50 instructions. To reach parallel processing by exploiting Instruction Level Parallelism (ILP), two-way... Viac o knihe
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O knihe
This book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS processor is designed using VHDL, which can execute 50 instructions. To reach parallel processing by exploiting Instruction Level Parallelism (ILP), two-way superscalar MIPS processor is designed by duplicating some components of single cycle MIPS processor and added hazard unit. Then, the single cycle MIPS processor subdivided to five pipeline stages 5-stages to obtain pipelined MIPS processor. To increase processor performance memory hierarchy is exploited by adding cache memory to pipeline MIPS processor. A Multicore MIPS processor is achieved by connecting two of complete single core together; these cores operate as separate independent processors within a single chip. Coherency problems are solved by using MESI protocol. All processors are designed using Xilinx ISE 13.4 Design Suite. The entire processor design is configured on a Xilinx Spartan-3AN FPGA starter kit, and the results have been displayed on the 2×16 LCD internal screen of the kit and external VGA screen.
- Vydavateľstvo: LAP LAMBERT Academic Publishing
- Rok vydania: 2017
- Formát: Paperback
- Rozmer: 220 x 150 mm
- Jazyk: Anglický jazyk
- ISBN: 9783330073845
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