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Anglický jazyk
Designing Reliable and Efficient Networks on Chips
Autor: Srinivasan Murali
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the... Viac o knihe
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O knihe
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
- Vydavateľstvo: Springer Netherlands
- Rok vydania: 2010
- Formát: Paperback
- Rozmer: 235 x 155 mm
- Jazyk: Anglický jazyk
- ISBN: 9789048182008
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