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Anglický jazyk
Low Power Asynchronous Logic design for Viterbi Decoders
Autor: T. Kalavathi Devi Sakthivel
This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous... Viac o knihe
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O knihe
This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.
- Vydavateľstvo: LAP LAMBERT Academic Publishing
- Rok vydania: 2018
- Formát: Paperback
- Rozmer: 220 x 150 mm
- Jazyk: Anglický jazyk
- ISBN: 9786139851294
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